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pin configurations 44-pin package 28-pin dip package rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a monolithic 12-bit quad dac ad664 features four complete voltage output dacs data register readback feature reset to zero override multiplying operation double-buffered latches surface mount and dip packages mil-std-883 compliant versions available applications automatic test equipment robotics process control disk drives instrumentation avionics one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: fax: product description the ad664 is four complete 12-bit, voltage-output dacs on one monolithic ic chip. each dac has a double-buffered input latch structure and a data readback function. all dac read and write operations occur through a single microprocessor-compatible i/o port. the i/o port accommodates 4-, 8- or 12-bit parallel words al- lowing simple interfacing with a wide variety of microprocessors. a reset to zero control pin is provided to allow a user to simulta- neously reset all dac outputs to zero, regardless of the contents of the input latch. any one or all of the dacs may be placed in a transparent mode allowing immediate response by the outputs to the input data. the analog portion of the ad664 consists of four dac cells, four output amplifiers, a control amplifier and switches. each dac cell is an inverting r-2r type. the output current from each dac is switched to the on-board application resistors and output amplifier. the output range of each dac cell is pro- grammed through the digital i/o port and may be set to unipo- lar or bipolar range, with a gain of one or two times the reference voltage. all dacs are operated from a single external reference. the functional completeness of the ad664 results from the combination of analog devices bimos ii process, laser-trimmed thin-film resistors and double-level metal interconnects. product highlights 1. the ad664 provides four voltage-output dacs on one chip offering the highest density 12-bit d/a function available. 2. the output range of each dac is fully and independently programmable. 3. readback capability allows verification of contents of the in- ternal data registers. 4. the asynchronous reset control returns all d/a outputs to zero volts. 5. dac-to-dac matching performance is specified and tested. 6. linearity error is specified to be 1/2 lsb at room tempera- ture and 3/4 lsb maximum for the k, b and t grades. 7. dac performance is guaranteed to be monotonic over the full operating temperature range. 8. readback buffers have tristate outputs. 9. multiplying-mode operation allows use with fixed or vari- able, positive or negative external references. 10. the ad664 is available in versions compliant with mil- std-883. refer to the analog devices military products databook or current ad664/883b data sheet for detailed specifications. 781/329-4700 781/461-3113 d
ad664Cspecifications (v ll = +5 v, v cc = +15 v, v ee = C15 v, v ref = +10 v, t a = +25 8 c unless otherwise noted) rev. C2C model jn/jp/ad/aj/sd kn/kp/bd/bj/be/td/te min typ max min typ max units resolution 12 12 * * bits analog output voltage range 1 uni versions 0 v cc C 2.0 2 * * volts bip versions v ee + 2.0 2 v cc C 2.0 2 * * volts output current 5 * ma load resistance 2 * k w load capacitance 500 * pf short-circuit current 25 40 * * ma accuracy gain error C7 3 7C 5 2 5 lsb unipolar offset C2 1/2 2C 1 1/4 1 lsb bipolar zero 3 C3 3/4 3C2 1/2 2 lsb linearity error 4 C3/4 1/2 3/4 C1/2 1/4 1/2 lsb linearity t min to t max C1 3/4 1 C3/4 1/2 3/4 lsb differential linearity C3/4 3/4 C1/2 1/2 lsb differential linearity t min to t max monotonic @ all temperatures monotonic @ all temperatures gain error drift unipolar 0 v to +10 v mode C12 7 12 C10 5 10 ppm of fsr 5 / c bipolar C5 v to +5 v mode C12 7 12 C10 5 10 ppm of fsr/ c bipolar C10 v to +10 v mode C12 7 12 C10 5 10 ppm of fsr/ c unipolar offset drift unipolar 0 v to +10 v mode C3 l.5 3C2 l 2 ppm of fsr/ c bipolar zero drift bipolar C5 v to +5 v mode C12 7 12 C10 5 10 ppm of fsr/ c bipolar C10 v to +10 v mode C12 7 12 C10 5 10 ppm of fsr/ c reference input input resistance 1.3 2. 6 * * k w voltage range 6 v ee + 2.0 2 v cc C 2.0 2 * * volts power reouirements v ll 4.5 5.0 5.5 * * * volts i ll @ v ih , v il = 5 v, 0 v 0.1 1 **m a @ v ih , v il = 2.4 v, 0.4 v 3 6 **m a v cc /v ee 6 11.4 6 16.5 * * volts i cc 12 15 **ma i ee 15 19 **ma total power 400 525 * * mw analog ground current 7 C600 400 +600 * * * m a matching performance gain 8 C6 3 6C4 2 4 lsb offset 9 C2 1/2 2C1 1/4 1 lsb bipolar zero 10 C3 1 3C2 1 2 lsb linearity 11 C1.5 1/2 1.5 C1 1/2 1 lsb crosstalk analog C90 * db digital C60 * db dynamic performance (r l = 2 k w , c l = 500 pf) settling time to 1/2 lsb off ? bits ? on, gain = 1, v ref = 10 8 10 * * m s settling time to 1/2 lsb C10 ? v ref ? 10 v, gain = 1, bits on 10 * m s glitch impulse 500 * nv-sec multiplying mode performance reference feedthrough @ 1 khz C75 * db reference C3 db bandwidth 70 * khz power supply gain sensitivity 11.4 v ? v cc ? 16.5 v 2 6 5 * * ppm/% C16.5 v ? v ee ? C11.4 v 2 6 5 * * ppm/% 4.5 v ? v ll ? 5.5 v 2 6 5 * * ppm/% d
ad664 model jn/jp/ad/aj/sd kn/kp/bd/bj/be/td/te min typ max min typ max units digital inputs v ih 2.0 * volts v il 0 0.8 * * volts data inputs i ih @ v in = v ll C10 1 10 ** * m a i il @ v in = dgnd C10 1 10 ** * m a cs /ds0/ds1/ rst / rd / ls i ih @ v in = v ll C10 1 10 ** * m a i il @ v in = v ll C10 1 10 ** * m a ms / tr 12 i ih @ v in = v ll C10 5 10 ** * m a i il @ v in = dgnd C10 C5 0 ** * m a qs0 / qsl / qs 2 l2 i ih @ v in = v ll C10 5 10 ** * m a i il @ v in = dgnd C10 1 10 ** * m a digital outputs v ol @ 1.6 ma sink 0.4 * volts v oh @ 0.5 ma source 2.4 * volts temperature range jn/jp/kn/kp 0 +70 ** c ad/aj/bd/bj/be C 40 +85 ** c sd/td/te C55 +125 ** c notes 1 a minimum power supply of 12.0 v is required for 0 v to +10 v and 10 v operation. a minimum power supply of 11.4 v is required for C5 v to +5 v operation. 2 for v cc < +12 v and v ee > C12 v. voltage not to exeeed 10 v maximum. 3 bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs. 4 linearity error is defined as the maximum deviation of the actual dac output from the ideal output (a straight line drawn from 0 to f.s. C 1 lsb). 5 fsr means full-scale range and is 20 v for 10 v range and 10 v for 5 v range. 6 a minimum power supply of 12.0 v is required for a 10 v reference voltage. 7 analog ground current is input code dependent. 8 gain error matching is the largest difference in gain error between any two dacs in one package. 9 offset error matching is the largest difference in offset error between any two dacs in one package. 10 bipolar zero error matching is the largest difference in bipolar zero error between any two dacs in one package. 11 linearity error matching is the difference in the worst ease linearity error between any two dacs in one package. 12 44-pin versions only. *specifications same as jn/jp/ad/aj/sd. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. absolute maximum ratings* v ll to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +7 v v cc to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +18 v v ee to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C18 v to 0 v soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c, 10 sec power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mw agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C1 v to +1 v reference input . . . . . . . . . . . . . . . . . . v ref 10 v and v ref (v cc C 2 v, v ee + 2 v) v cc to v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 v caution esd (electrostatic discharge) sensitive device. unused devices must be stored in conductive foam or shunts. the protective foam should be discharged to the destination socket before devices are removed. warning! esd sensitive device digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v analog outputs . . . . . . . . . . . . . . . . . . . . . indefinite shorts to v cc, v ll , v ee and gnd *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rev. C3C d
ad664 rev. C4C figure 1a. 44-pin block diagram functional description the ad664 combines four complete 12-bit voltage output d/a converters with a fast, flexible digital input/output port on one monolithic chip. it is available in two forms, a 44-pin version shown in figure 1a and a 28-pin version shown in figure 1b. 44-pin versions each dac offers flexibility, accuracy and good dynamic perfor- mance. the r-2r structure is fabricated from thin-film resistors which are laser-trimmed to achieve 1/2 lsb linearity and guar- anteed monotonicity. the output amplifier combines the best features of the bipolar and mos devices to achieve good dy- namic performance and low offset. settling time is under 10 m s and each output can drive a 5 ma, 500 pf load. short-circuit protection allows indefinite shorts to v ll , v cc , v ee and gnd. the output and span resistor pins are available separately. this feature allows a user to insert current-boosting elements to in- crease the drive capability of the system, as well as to overcome parasitics. digital circuitry is implemented in cmos logic. the fast, low power, digital interface allows the ad664 to be interfaced with most microprocessors. through this interface, the wide variety of features on each chip may be accessed. for example, the in- put data for each dac is programmed by way of 4-, 8-, 12- or 16-bit words. the double-buffered input structure of this latch allows all four dacs to be updated simultaneously. a readback feature allows the internal registers to be read back through the same digital port, as either 4-, 8- or 12-bit words. when dis- abled, the readback drivers are placed in a high impedance (tristate) mode. a transparent mode allows the input data to pass straight through both ranks of input registers and appear at the dac with a minimum of delay. one d/a may be placed in the transparent mode at a time, or all four may be made transparent at once. the mode select feature allows the output range and mode of the dacs to be selected via the data bus inputs. an internal mode select register stores the selec- tions. this register may also be read back to check its contents. a reset-to-zero feature allows all dacs to be reset to 0 volts out by strobing a single pin. figure 1b. 28-pin block diagram 28-pin versions the 28-pin versions are dedicated versions of the 44-pin ad664. each offers a reduced set of features from those offered in the 44-pin version. this accommodates the reduced number of package pins available. data is written and read with 12-bit words only. output range and mode select functions are also not available in 28-pin versions. as an alternative, users specify either the uni (unipolar, 0 to v ref ) models or the bip (bipolar, Cv ref to v ref ) models depending on the application require- ments. finally, the transparent mode is not available on the 28-pin versions. d
ad664 rev. C5C table i. transfer functions mode = uni mode = bip 000000000000 = 0 v 000000000000 = C v ref /2 gain = 1 100000000000 = v ref /2 100000000000 = 0 v 111111111111 = v ref C 1 lsb 111111111111 = v ref /2 C1 lsb 000000000000 = 0 v 000000000000 = v ref gain = 2 100000000000 = v ref 100000000000 = 0 v 111111111111 = 2 v ref C 1 lsb 111111111111 = +v ref C 1 lsb definitions of specifications linearity error: analog devices defines linearity error as the maximum deviation of the actual, adjusted dac output from the ideal analog output (a straight line drawn from 0 to fs C 1 lsb) for any bit combination. this is also referred to as relative accuracy. the ad664 is laser-trimmed to typically maintain linearity errors at less than 1/4 lsb. monotonicity: a dac is said to be monotonic if the out- put either increases or remains constant for increasing digital inputs such that the output will always be a nondecreasing func- tion of input. all versions of the ad664 are monotonic over their full operating temperature range. differential linearity: monotonic behavior requires that the differential linearity error be less than 1 lsb both at 25 c as well as over the temperature range of interest. differen- tial nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digi- tal input code. for example, for a 10 v full-scale output, a change of 1 lsb in digital input code should result in a 2.44 mv change in the analog output (v ref = 10 v, gain = 1, 1 lsb = 10 v 1/4096 = 2.44 mv). if in actual use, however, a 1 lsb change in the input code results in a change of only 0.61 mv (1/4 lsb) in analog output, the differential non- linearity error would be C1.83 mv, or C3/4 lsb. gain error: dac gain error is a measure of the difference between the output span of an ideal dac and an actual device. unipolar offset error: unipolar offset error is the dif- ference between the ideal output (0 v) and the actual output of a dac when the input is loaded with all 0s and the mode is unipolar. bipolar zero error: bipolar zero error is the difference between the ideal output (0 v) and the actual output of a dac when the input code is loaded with the msb = 1 and the rest of the bits = 0 and the mode is bipolar. settling time: settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the digital input transition. crosstalk: crosstalk is the change in an output caused by a change in one or more of the other outputs. it is due to capacitive and thermal coupling between outputs. reference feedthrough: the portion of an ac refer- ence signal that appears at an output when all input bits are low. feedthrough is due to capacitive coupling between the reference input and the output. it is specified in decibels at a particular frequency. reference 3 db bandwidth: the frequency of the ac reference input signal at which the amplitude of the full-scale output response falls 3 db from the ideal response. glitch impulse: glitch impulse is an undesired output voltage transient caused by asymmetrical switching times in the switches of a dac. these transients are specified by their net area (in nv-sec) of the voltage vs. time characteristic. pin configurations 28-pin dip package 44-pin package d
ad664 rev. C6C analog circuit considerations grounding recommendations the ad664 has two pins, designated analog and digital ground. the analog ground pin is the high quality ground ref- erence point for the device. a unique internal design has resulted in low analog ground current. this greatly simplifies management of ground current and the associated induced volt- age drops. the analog ground pin should be connected to the analog ground point in the system. the external reference and any external loads should also be returned to analog ground. the digital ground pin should be connected to the digital ground point in the circuit. this pin returns current from the logic portions of the ad664 circuitry to ground. analog and digital grounds should be connected at one point in the system. if there is a possibility that this connection be bro- ken or otherwise disconnected, then two diodes should be con- nected between the analog and digital ground pins of the ad664 to limit the maximum ground voltage difference. power supplies and decoupling the ad664 requires three power supplies for proper operation. v ll powers the logic portions of the device and requires +5 volts. v cc and v ee power the remaining portions of the cir- cuitry and require +12 v to +15 v and C12 v to C15 v, respec- tively. v cc and v ee must also be a minimum of two volts greater then the maximum reference and output voltages anticipated. decoupling capacitors should be used on all power supply pins. good engineering practice dictates that the bypass capacitors be located as near as possible to the package pins. v ll should be bypassed to digital ground. v cc and v ee should be decoupled to analog ground. driving the reference input the reference input of the ad664 can have an impedance as low as 1.3 k w . therefore, the external reference voltage must be able to source up to 7.7 ma of load current. suitable choices include the 5 v ad586, the 10 v ad587 and the 8.192 v ad689. the architecture of the ad664 derives an inverted version of the reference voltage for some portions of the internal circuitry. this means that the power supplies must be at least 2 v figure 2. recommended circuit schematic greater than both the external reference and the inverted exter- nal reference. output considerations each dac output can source or sink 5 ma of current to an external load. short-circuit protection limits load current to a maximum load current of 40 ma. load capacitance of up to 500 pf can be accommodated with no effect on stability. should an application require additional output current, a cur- rent boosting element can be inserted into the output loop with no sacrifice in accuracy. figure 3 details this method. figure 3. current-boosting scheme ad664 output voltage settling time is 10 m s maximum. figure 4 shows the output voltage settling time with a fixed 10 v refer- ence, gain = 1 and all bits switched from 1 to 0. figure 4. settling time; all bits switched from on to off alternately, figure 5 shows the settling characteristics when the reference is switched and the input bits remain fixed. in this case, all bits are on, the gain is 1 and the reference is switched from C5 v to +5 v. figure 5. settling time; input bits fixed, reference switched d
ad664 rev. C7C multiplying mode performance figure 6 illustrates the typical open-loop gain and phase perfor- mance of the output amplifiers of the ad664. gain ?db 0 +5 +20 +15 +10 10k 100k 1m 0 +45 +90 phase margin ?degrees frequency ?h z gain phase figure 6. gain and phase performance of ad664 outputs crosstalk crosstalk is a spurious signal on one dac output caused by a change in the output of one or more of the other dacs. crosstalk can be induced by capacitive, thermal or load current induced feedthrough. figure 7 shows typical crosstalk. dac b is set to output 0 volts. the outputs of dac a, c and d switch 2 k w loads from 10 v to 0 v. the first disturbance in the output of dac b is caused by digital feedthrough from the input data lows. the second disturbance is caused by analog feedthrough from the other dac outputs. figure 7. output crosstalk output noise wideband output noise is shown in figure 8. this measurement was made with a 7 mhz noise bandwidth, gain = 1 and all bits on. the total rms noise is approximately one fifth the visual peak-to-peak noise. digital interface as table ii shows, the ad664 makes a wide variety of operating modes available to the user. these modes are accessed or pro- grammed through the high speed digital port of the quad dac. on-board registers program and store the dac input codes and the dac operating mode data. all registers are double-buffered to allow for simultaneous updating of all outputs. register data may be read back to verify the respective contents. the digital port also allows transparent operation. data from the input pins can be sent directly through both ranks of latches to the dac. figure 8. typical output noise partial address decoding is performed by the ds0, ds1, qs0 , qs1 and qs2 address bits. qs0 , qs1 and qs2 allow the 44-pin versions of the ad664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words. the rst pin provides a simple method to reset all output voltages to zero. its advantages are speed and low software overhead. input data in general, two types of data will be input to the registers of the ad664, input code data and mode select data. input code data sets the dac inputs while the mode select data sets the gain and range of each dac. the versatile i/o port of the ad664 allows many different types of data input schemes. for example, the input code for just one of the dacs may be loaded and the output may or may not be updated. or, the input codes for all four dacs may be written, and the outputs may or may not be updated. the same applies for mode selection. the mode of just one or many of the dacs may be rewritten and the user can choose to immediately update the outputs or wait until a later time to transfer the mode information to the outputs. a user may also write both input code and mode information into their respective first ranks and then update all second ranks at once. finally, transparent operation allows data to be transferred from the inputs to the outputs using a single control line. this feature is useful, for example, in a situation where one of the dacs is used in an a/d converter. the sar register could be connected directly to a dac by using the transparent mode of operation. another use for this feature would be during system calibration where the endpoints of the transfer function of each dac would be measured. for example, if the full-scale voltages of each dac were to be measured, then by making all four dacs transparent and putting all 1s on the input port, all four dacs would be at full-scale. this requires far less software overhead than loading each register individually. d
ad664 rev. C8C table ii. ad664 digital truth table function ds1, ds0 ls ms tr qs0 , 1 , 2 1 rd cs rst load 1st rank (data) daca 00 0 1 1 select quad 1 1 ? 01 dacb 01 0 1 1 select quad 1 1 ? 01 dacc 10 0 1 1 select quad 1 1 ? 01 dacd 11 0 1 1 select quad 1 1 ? 01 load 2nd rank (data) xx 1 1 1 xxx 1 1 ? 01 readback 2nd rank (data) select d/a x 1 1 select quad 0 1 ? 01 reset xx x x x xxx x x 0 transparent 1 all dacs xx 1 1 0 000 1 1 ? 01 daca 00 0 1 0 000 1 1 ? 01 dacb 01 0 1 0 000 1 1 ? 01 dacc 10 0 1 0 000 1 1 ? 01 dacd 11 0 1 0 000 1 1 ? 01 mode select 1, 2 1st rank xx 0 0 1 00x 1 1 ? 01 2nd rank xx 1 0 1 xxx 1 1 ? 01 readback mode 1 xx x0100x 01 ? 01 update 2nd rank and mode xx 1 0 0 xxx 1 1 ? 01 notes x = dont care. 1 for 44-pin versions only. allow the ad664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words. 2 for ms , tr , ls = 0, a ms 1st write occurs. figure 9a. update output of a single dac 25 8 ct min to t max symbol min (ns) min (ns) t ls *0 0 t ds 00 t dh 00 t lw 60 80 t ch 30 50 t as 00 t ah 00 *for t ls > 0, the width of ls must be increased by the same amount that t ls is greater than 0 ns. figure 9b. update output of a single dac timing the following sections detail the timing requirements for various data loading schemes. all of the timing specifica- tions shown assume v ih = 2.4 v, v il = 0.4 v, v cc = +15 v, v ee = C15 v and v ll = +5 v . load and update one dac output in this first example, the object is simply to change the output of one of the four dacs on the ad664 chip. the procedure is to select the address bits that indicate the dac to be programmed, pull latch select ( ls ) low, pull chip select ( cs ) low, release ls and then release cs . when cs goes low, data enters the first rank of the input latch. as soon as ls goes high, the data is transferred into the second rank and produces the new output voltage. during this transfer, ms , tr , rd and rst should be held high. preloading the first rank of one dac in this case, the object is to load new data into the first rank of one of the dacs but not the output. as in the previous case, the address and data inputs are placed on the appropriate pins. ls is then brought to 0 and then cs is asserted. note that in this situation, however, cs goes high before ls goes high. the in- put data is prevented from getting to the second rank and affect- ing the output voltage. d
ad664 rev. C9C figure 10a. preload first rank of a dac 25 8 ct min to t max symbol min (ns) min (ns) t ls 00 t lh 15 15 t cw 80 100 t ds 00 t dh 15 15 t as 00 t ah 15 15 figure 10b. preload first rank of a dac timing this allows the user to preload the data to a dac and strobe it into the output latch at some future time. the user could do this by reproducing the sequence of signals illustrated in the next section. update second rank of a dac assuming that a new input code had previously been placed into the first rank of the input latches, the user can update the out- put of the dac by simply pulling cs low while keeping ls , ms , tr , rd and rst high. address data is not needed in this case. in reality, all second ranks are being updated by this pro- cedure, but only those which receive data different from that already there would manifest a change. updating the second rank does not change the contents of the first rank. figure 11. update second rank of a dac the same options that exist for individual dac input loading also exist for multiple dac input loading. that is, the user can choose to update the first and second ranks of the registers or preload the first ranks and then update them at a future time. preload multiple first rank registers the first ranks of the dac input registers may be preloaded with new input data without disturbing the second rank data. this is done by transferring the data into the first rank by bring- ing cs low while ls is low. but cs must return high before ls . this prevents the data from the first rank from getting into the second rank. a simple second rank update cycle as shown in figure 11 would move the preloaded information to the dacs. figure 12. preload first rank registers load and update multiple dac outputs the following examples demonstrate two ways to update all dac outputs. the first method involves doing all data transfers during one long cs low period. note that in this case, shown in figure 13, ls returns high before cs goes high. data hold time, relative to an address change, is 70 ns. this updates the outputs of all dacs simultaneously. figure 13. update all dac outputs the second method involves doing a cs assertion (low) and an ls toggle separately for each dac. it is basically a series of preload operations (figure 10). in this case, illustrated in figure 14, two ls signals are shown. one, labeled ls , goes high before cs returns high. this transfers the new input word to the dac outputs sequentially. the second ls signal, labeled alter- nate ls , stays low until cs returns high. using this sequence loads the first ranks with each new input word but doesnt up- date the dac outputs. to then update all dac outputs simul- taneously would require the signals illustrated in figure 11. figure 14. load and update multiple dacs selecting gain range and modes (44-pin versions) the ad664s mode select feature allows a user to configure the gain ranges and output modes of each of the four dacs. on-board switches take the place of up to eight external relays that would normally be required to accomplish this task. the switches are programmed by the mode select word entered via the data i/o port. the mode select word is eight-bits wide and d
ad664 rev. C10C occupies the topmost eight bits of the input word. the last four bits of the input word are dont cares. figure 15 shows the format of the mode select word. the first four bits determine the gain range of the dac. when set to be a gain of 1, the output of the dac spans a voltage of 1 times the reference. when set to a gain of 2, the output of the dac spans a voltage of 2 times the reference. the next four bits determine the mode of the dac. when set to unipolar, the output goes from 0 to ref or 0 to 2 ref. when the bipolar mode is selected, the output goes from Cref/2 to ref/2 or Cref to ref. figure 15. mode select word format load and update mode of one dac in this next example, the object is to load new mode informa- tion for one of the dacs into the first rank of latches and then immediately update the second rank. this is done by putting the new mode information (8-bit word length) onto the databus. then ms and ls are pulled low. following that, cs is pulled low. this loads the mode information into the first rank of latches. ls is then brought high. this action updates the second rank of latches (and, therefore, the dac outputs). the load cycle ends when cs is brought high. in reality, this load cycle really updates the modes of all the dacs, but the effect is to only change the modes of those dacs whose mode select information has actually changed. figure 16a. load and update mode of one dac 25 8 ct min to t max symbol min (ns) min (ns) t ms 00 t ls *0 0 t ds 00 t lw 60 70 t ch 70 80 t dh 00 t mh 00 *for t ls > 0, the width of ls must be increased by the same amount that t ls is greater than 0 ns. figure 16b. load and update mode of one dac timing preloading the mode select register mode data can be written into the first rank of the mode select latch without changing the modes currently being used. this feature is useful when a user wants to preload new mode infor- mation in anticipation of strobing that in at a future time. fig- ure 17 illustrates the correct sequence and timing of control signals to accomplish this task. this allows the user to preload the data to a dac and strobe it into the output latch at some future time. the user could do this by reproducing the sequence of signals illustrated in figures 17c and 17d. figure 17a. preload mode select register figure 17b. preload mode select register timing 1 0 1 0 data input/output bits address qs0,qs1,qs2 ds0,ds1 _________ __ ms __ cs t ms t mh t w figure 17c. update second rank of mode select latch 25 8 ct min to t max symbol min (ns) min (ns) t ms 00 t mh 00 t w 80 100 figure 17d. update second rank of mode select latch timing transparent operation (44-pin versions) transparent operation allows data from the inputs of the ad664 to be transferred into the dac registers without the intervening step of being latched into the first rank of latches. two modes of transparent operation exist, the partially trans- parent mode and a fully transparent mode. in the partially transparent mode, one of the dacs is transparent while the remaining three continue to use the data latched into their respective input registers. both modes require a 12-bit wide input word! d
ad664 rev. C11C output data two types of outputs may be obtained from the internal data registers of the ad664 chip, mode select and dac input code data. readback data may be in the same forms in which it can be entered; 4-, 8-, and 12-bit wide words (12 bits only for 28-pin versions). dac data readback dac input code readback data is obtained by setting the address of the dac (ds0, ds1) and quads ( qs0 , qs1 , qs2 ) on the address pins and bringing the rd and cs pins low. the timing diagram for a dac code readback operation appears in figure 20. figure 20a. dac input code readback 25 ct min to t max symbol min (ns) min (ns) t as 00 t rs 00 t dv 150 180 t df 60 75 t ah 00 t rh 00 figure 20b. dac input code readback timing mode data readback mode data is read back in a similar fashion. by setting ms , qs0 , qs1 , rd and cs low while setting tr and rst high, the mode select word is presented to the i/o port pins. figure 21 shows the timing diagram for a readback of the mode select data register. figure 21a. mode data readback 25 8 ct min to t max symbol min (ns) min (ns) t as 00 t ms 00 t dv 150 180 t df 60 75 t ah 00 t mh 00 figure 21b. dac mode readback timing fully transparent operation can be thought of as a simultaneous load of data from figure 9a where replacing ls with tr causes all 4 dacs to be loaded at once. the fully transparent mode is achieved by asserting lows on qs0 , qs1 , qs2 , tr and cs while keeping ls high in addition to ms and rb . figure 18a illustrates the necessary timing rela- tionships. fully transparent operation will also work with tr tied low (enabled). data input/ output bits t ts t ds t qh t dh t qs data valid tw t t ch 1 ls qs tr cs figure 18a. fully transparent mode 25 8 ct min to t max symbol min (ns) min (ns) t as 00 t qs 00 t ts *0 0 t tw 80 90 t ch 90 110 t dh 00 t qh 00 *for t ts > 0, the width of tr must be increased by the same amount that t ts is greater than 0 ns. figure 18b. fully transparent mode timing partially transparent operation can be thought of as preloading the first rank in figure 10a without requiring the additional cs pulse from figure 11. the partially transparent mode is achieved by setting cs , qs0 , qs1 , qs2 , ls , and tr low while keeping rd and ms high. the address of the transparent dac is asserted on ds0 and ds1. figure 19a illustrates the necessary timing relationships. partially transparent operation will also work with tr tied low (enabled). data input/ output bits address qs0, qs1, qs2 ds0, ds1, ls t ts t as t dh data valid w t t th tr cs address valid t ah t ds figure 19a. partially transparent 25 ct min to t max symbol min (ns) min (ns) t ds 00 t as 00 t ts 00 t w 90 110 t dh 15 15 t ah 15 15 t th 15 15 figure 19b. partially transparent mode timing d
ad664 rev. C12C output loads readback timing is tested with the output loads shown in figure 22. figure 22. output loads asynchronous reset operation the asynchronous reset signal shown in figure 23 may be asserted at any time. a minimum pulse width (t rw ) of 90 ns is required. the reset feature is designed to return all dac out- puts to 0 volts regardless of the mode or range selected. in the 44-pin versions, the modes are reset to unipolar 10 v span (gain of 1), and the input codes are rewritten to be 0s. previous dac code and mode information is erased. figure 23a. asynchronous reset operation figure 23b. asynchronous reset operation timing in the 28-pin versions of the ad664, the mode remains unchanged, the appropriate input code is rewritten to reset the output voltage to 0 volts. as in the 44-pin versions, the previous input data is erased. at power-up, an ad664 may be activated in either the read or write modes. while at the device level this will not produce any problems, at the system level it may. analog devices recom- mends the addition of a simple power-on reset scheme to any system where the possibility of an unknown start-up state could be a problem. the simplest version of this scheme is illustrated in figure 24. ad664 ad664 +5v 10k w 100nf #1 rst #n rst figure 24. power-on reset it is obvious from inspection that the scheme shown in figure 24 is only appropriate for systems in which the rst is otherwise not used. should the user wish to use the rst pin, an addi- tional logic gate may be included to combine the power-on reset with the reset signal. interfacing the ad664 to microprocessors the ad664 is easy to interface with a wide variety of popular microprocessors. common architectures include processors with dedicated 8-bit data and address buses, an 8-bit bus over which data and address are multiplexed, an 8-bit data and 16-bit address partially muxed, and separate 16-bit data and address buses. ad664 addressing can be accomplished through either memory-mapped or i/o techniques. in memory-mapped schemes, the ad664 appears to the host microprocessor as ram memory. standard memory addressing techniques are used to select the ad664. in the i/o schemes, the ad664 is treated as an external i/o device by the host. dedicated i/o pins are used to address the ad664. mc6801 interface in figures 25aC25d, we illustrate a few of the various methods that can be used to connect an ad664 to the popular mc6801 microprocessor. in each of these cases, the mc6801 is intended to be configured in its expanded, nonmultiplexed mode of operation. in this mode, the mc6801 can address 256 bytes of external memory over 8-bit data (port 3) and 8-bit address (port 4) buses. eight general-purpose i/o lines (port 1) are also available. on-board ram and rom provide program and data storage space. in figure 25a, the three least significant address bits (p40, p41 and p42) are employed to select the appropriate on-chip addresses for the various input registers of the ad664. three i/o lines (p17, p16 and p15) are used to select various operat- ing features of the the ad664. ios and e(nable) are combined to produce an appropriate cs signal. this addressing scheme leaves the five most significant address bits and five i/o lines free for other tasks in the system. figure 25b shows another way to interface an ad664 to the mc6801. here weve used the six least significant address lines to select ad664 features and registers. this is a purely memory- mapped scheme while the one illustrated in figure 25a uses some memory-mapping as well as some dedicated i/o pins. in figure 25b, two address lines and all eight i/o lines remain free for other system tasks. d
ad664 rev. C13C figure 25a. simple ad664 to mc6801 interface expansion of the scheme employed in figure 25a results in that shown in figure 25c. here, two ad664s are connected to an mc6801, providing a total of eight 12-bit, software program- mable dacs. again, the three least significant bits of address are used to select the on-chip registers of the ad664. ios and e, as well as a fourth address bit, are decoded to provide the appropriate cs signals. four address and five i/o lines remain uncommitted. a slightly more sophisticated approach to system expansion is illustrated in figure 25d. here, a 74ls138 (1-of-8 decoder) is used to address one of the eight ad664s connected to the mc6801. the three least significant address bits are used to select on-chip register and dac. the next three address bits are used to select the appropriate ad664. ios and e gate the 74ls138 output. figure 25b. alternate ad664 to mc6801 interface figure 25c. interfacing two ad664s to an mc6801 d
ad664 rev. C14C the schemes in figure 25 illustrate some of the trade-offs which a designer may make when configuring a system. for example, the designer may use i/o lines instead of address bits or vice versa. this decision may be influenced by other i/o tasks or sys- tem expansion requirements. he/she can also choose to imple- ment only a subset of the features available. perhaps the rst pin isnt really needed. tying that input pin to v logic frees up another i/o or address bit. the same consideration applies to mode select. in all of these cases tr is shown tied to v logic , because the mc6801 cannot provide the 12-bit-wide input word required for the transparent mode. in situations where transparent operation isnt required, and mode select is also not needed, the designer may consider specifying the dip version of the device (either the uni or bip version). each of the schemes illustrated in figure 25 operates with an mc6801 at clock rates up to and including 1.5 mhz. similar schemes can be derived for other 8-bit microprocessors and microcontrollers such as the 8051/8086/8088/6502, etc. one such scheme developed for the 8051/ad664 is illustrated in figure 26. 8051 interface figure 26 shows the ad664 combined with an 8051 m controller chip. three lsbs of address provide the quad and dac select signals. control signals from port 1 select various operating modes such as readback, mode select and reset as well as pro- viding the ls signal. read and write signals from the 8051 are decoded to provide the cs signal. figure 25d. interfacing eight ad664s to an mc6801 d
ad664 rev. C15C ibm pc* interface figure 27 illustrates a simple interface between an ibm pc and an ad664. the three least significant address bits are used to select the quad and dac. the next two address bits are used for ls and ms . in this scheme, a 12-bit input word requires two load cycles, an 8-bit word and a 4-bit word. another write is required to transfer the word or words previously written to the second rank. a 12-bit-wide word again requires at least two read cycles; one for the 8 msbs and four for the lsbs. the page select signal produces a cs strobe for any address from 300h to 31fh. figure 26. ad664 to 8051 interface figure 27. ad664 to ibm pc interface *ibm pc is a trademark of international business machines corp. d
ad664 rev. C16C table iii details the memory locations and addresses used by this interface. table iii. ibm pc memory map hex a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 register selected 30011000000 0 0 illegal address 301 0 0 1 mode select, 1st rank 302 0 1 0 illegal address 303 0 1 1 mode select, 1st rank 304 1 0 0 illegal address 305 1 0 1 mode select, 1st rank 306 1 1 0 illegal address 307 t 1 1 1 mode select, 1st rank 308 1 0 0 0 mode select, 2nd rank 309 0 0 1 30a 0 1 0 30b 0 1 1 30c 1 0 0 30d 1 0 1 30e 1 1 0 30f tt 11 1 t 310 1 0 0 0 0 dac a, 4 lsbs, 1st rank 311 0 0 1 dac a, 8 msbs, 1st rank 312 0 1 0 dac b, 4 lsbs, 1st rank 313 0 1 1 dac b, 8 msbs, 1st rank 314 1 0 0 dac c, 4 lsbs, 1st rank 315 1 0 1 dac c, 8 msbs, 1st rank 316 1 1 0 dac d, 4 lsbs, 1st rank 317 t 1 1 1 dac d, 8 msbs, 1st rank 318 1 0 0 0 2nd rank 319 0 0 1 31a 0 1 0 31b 0 1 1 31c 1 0 0 31d 1 0 1 31e 1 1 0 31f ttttttt 11 1 t note: shaded registers are readable. d
ad664 rev. C17C the following ibm pc basic routine produces four output volt- age ramps from one ad664. line numbers 10 through 70 de- fine the hardware addresses for the first and second ranks of dac registers as well as the first and second ranks of the mode select register. program variables are initialized in line numbers 110 through 130. line number 170 writes 0s out to the first rank and, then, the second rank of the mode select register. line numbers 200 through 320 calculate output voltages. fi- nally line numbers 410 through 450 update the first, then the second ranks of the dac input registers. hardware registers may be read with the inp instruction. for example, the con- tents of the dac a register may be accessed with the following com mand: line# a = inp(daca). 5 rem----ad664 lissajous patterns---- 10 rem ---assign hardware addresses--- 20 daca = 785 30 dacb = 787 40 dacc = 789 50 dacd = 791 60 dac2nd = 792 70 mode1 = 769: mode2 = 776 80 rem 90 rem 100 rem ---initialize variables--- 110 x = 0: y1 = 128: y2 = 64: y3 = 32 120 cx = 1: cy1 = 1: cy2 = -1: cy3= 1 130 fx = 9: fy1 = 5: fy2 = 13: fy3 = 15 140 rem 150 rem 160 rem ---initialize modes and gains--- 170 out mode1,0: out mode2,0 180 rem 190 rem 200 rem ---calculate variables--- 210 x = x + fx*cx 220 y1 = y1 + fy1*cy1 230 y2 = y2 + fy2*cy2 240 y3 = y3 + fy3*cy3 250 if x > 255 then x = 255: cx = -1: goto 270 260 if x < 0 then x = 0: cx = 1 270 if y1 > 255 then y1 = 255: cy1 = -1: goto 290 280 if y1 < 0 then y1 = 0: cy1 = 1 290 if y2 > 255 then y2 = 255: cy2 = -1 goto 310 300 if y2 < 0 then y2 = 0: cy2 = -1 310 if y3 > 255 then y3 = 255: cy3 = -1: goto 400 320 if y3 < 0 then y3 = 0: cy3 = 1 330 rem 340 rem 400 rem ---send dac data--- 410 out daca,x 420 out dacb,yl 430 out dacc,y2 440 out dacd,y3 450 out dac2nd,0 500 rem 510 rem 520 rem ---loop back--- 530 goto 210 d
ad664 rev. C18C simple ad664 to mc68000 interface figure 28 shows an ad664 connected to an mc68000. in this memory-mapped i/o scheme, the left-justified data is written in one 12-bit input word. four address bits are used to perform the on-chip d/a selection as well as the various operating fea- tures. the r/ w signal controls the rd function and system reset controls rst . this scheme can be converted to write right-justified data by connecting the data inputs to data bits d0 through d11 respectively. other options include controlling the qs0 , qs1 and qs2 pins with uds and lds to provide a way to write 8-bit input and read 8-bit output words. figure 28. ad664 to mc68000 interface d
ad664 rev. C19C figure 29. ad664 in tester-per-pin architecture applications of the ad664 tester-per-pin ate architecture figure 29 shows the ad664 used in a single channel of a digital test system. in this scheme, the ad664 supplies four individual output voltages. two are provided to the v high and v low in- puts of the ad345 pin driver i.c. to set the digital output levels. two others are routed to the inputs of the ad96687 dual com- parator to supply reference levels of the readback features. this approach can be replicated to give as many channels of stimulus/ readback as the tester has pins. the ad664 is a particularly appropriate choice for a large-scale system because the low power requirements (under 500 mw) ease power supply and cooling requirements. analog ground currents of 600 m a or less make the ground current management task simpler. all dacs can be driven from the same system reference and will track over time and temperature. finally, the small board area required by the ad664 (and ad345 and ad96687) allows a high functional density. x-y plotters figure 30 is a block diagram of the control section of a microprocessor-controlled x-y pen plotter. in this conceptual exercise, two of the dacs are used for the x-channel drive and two are used for the y-channel drive. each provides either the coarse or fine movement control for its respective channel. this approach offers increased resolution over some other approaches. a designer can take advantage of the reset feature of the ad664 in the following manner. if the system is designed such that the home position of the pen (or galvanometer, beam, head or similar mechanism) results when the outputs of all of the dacs are at zero, then no system software is required to home the pen. a simple reset signal is sufficient. similarly, the transparent feature could be used to the same end. one code can be sent to all dacs at the same time to send the pen to the home position. of course, this would require some software where the previous example would require only a single reset strobe signal! drawing scaling can be achieved by taking advantage of the ad664s software programmable gain settings. if, for example, an a size drawing is created with gain settings of 1, then a c size drawing can be created by simply resetting all dac gains to 2 and redrawing the object. conversely, a c size drawing created with gains of 2 can be reduced to a size sim- ply by changing the gains to 1 and redrawing. the same princi- pal applies for conversion from b size to d size or d size to b size. the multiplying capability of the ad664 provides another scaling option. changing the reference voltage provides a proportional change in drawing size. inverting the reference voltage would invert the drawing. swapping digital input data from the x channel to the y chan- nel would rotate the drawing 90 degrees. figure 30. x-y plotter block diagram d
ad664 C20C rev. d outline dimensions figure 31. 28-lead side-brazed cera mic dual in-line package [sbdip] (d-28-2) dimensions shown in inches and (millimeters) figure 32. 28-lead plastic dual in-line package [pdip] wide body (n-28-2) dimensions shown in inches and (millimeters) 28 1 4 15 0.610 (15.49) 0.580 (12.73) pin 1 0.100 (2.54) max 0.005 (0.13) min seating plane 0.026 (0.66) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.085 (2.16) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) min 1.490 (37.85) max 0.100 (2.54) 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off i nch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole leads. compliant to jedec standards ms-011 071006-a 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.050 (1.27) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 114 15
ad664 rev. d C21C figure 33. 44-terminal ceramic leadless chip carrier [lcc] (e-44-1) dimensions shown in inches and (millimeters) figure 34. 44-lead ceramic leaded chip carrier, j-formed leads [jlcc] (j-44) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 1 44 6 7 18 17 39 40 bottom view 29 28 0.055 (1.40) 0.045 (1.14) 0.662 (16.82) 0.640 (16.27) sq 0.028 (0.71) 0.022 (0.56) 0.020 (0.51) ref ? 45 0.040 (1.02) ref ? 45 3 places 0.050 (1.27) bsc 0.075 (1.91) ref 0.100 (2.54) 0.064 (1.63) 022106-a controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 40 29 28 18 17 7 39 pin 1 top view 6 0.662 (16.82) 0.628 (15.95) sq 0.700 (17.78) 0.680 (17.27) sq 0.050 (1.27) bsc 0.500 (12.70) 0.492 (12.50) 0.650 (16.51) 0.610 (15.49) 0.023 (0.58) 0.013 (0.33) 0.025 (0.64) min 0.078 (1.98) 0.054 (1.37) 0.135 (3.43) 0.100 (2.54) 0.032 (0.81) 0.020 (0.51) bottom view pin 1 index 0.065 (1.65) 0.040 (1.02) ref ? 45 3 places 0.020 (0.51) ref ? 45
ad664 C22C rev. d figure 35. 44-lead plastic leaded chip carrier [plcc] (p-44) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option 5962-8871901mxa ?55c to +125c 28-lead side-brazed sbdip d-28-2 5962-8871902mxa ?55c to +125c 28-lead side-brazed sbdip d-28-2 5962-8871903mya ?55c to +125c 44-lead lcc e-44-1 ad664ad-bip ?40c to +85c 28-lead side-brazed sbdip d-28-2 ad664ad-uni ?40c to +85c 28-lead side-brazed sbdip d-28-2 ad664aj ?40c to +85c 44-lead jlcc j-44 ad664bd-bip ?40c to +85c 28-lead side-brazed sbdip d-28-2 ad664bd-uni ?40c to +85c 28-lead side-brazed sbdip d-28-2 ad664be ?40c to +85c 44-lead lcc e-44-1 ad664bj ?40c to +85c 44-lead jlcc j-44 ad664jn-bip 0c to +70c 28-lead pdip n-28-2 ad664jn-uni 0c to +70c 28-lead pdip n-28-2 ad664jnz-bip 0c to +70c 28-lead pdip n-28-2 ad664jnz-uni 0c to +70c 28-lead pdip n-28-2 ad664jp 0c to +70c 44-lead plcc p-44 ad664jpz 0c to +70c 44-lead plcc p-44 ad664kn-bip 0c to +70c 28-lead pdip n-28-2 ad664knz-bip 0c to +70c 28-lead pdip n-28-2 ad664knz-uni 0c to +70c 28-lead pdip n-28-2 ad664kp 0c to +70c 44-lead plcc p-44 ad664kpz 0c to +70c 44-lead plcc p-44 ad664sd-bip ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664sd-bip/883b ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664sd-uni ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664sd-uni/883b ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664td-bip ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664td-bip/883b ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664td-uni/883b ?55c to +125c 28-lead side-brazed sbdip d-28-2 ad664te/883b ?55c to +125c 44-lead lcc e-44-1 ad664tj/883b ?55c to +125c 44-lead jlcc j-44 1 z = rohs compliant part. compliant to jedec standards mo-047-ac controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. bottom view (pins up) 6 7 40 39 17 18 29 28 top view (pins down) 0.656 (16.66) 0.650 (16.51) sq 0.048 (1.22) 0.042 (1.07) 0.050 (1.27) bsc 0.695 (17.65) 0.685 (17.40) sq 0.048 (1.22) 0.042 (1.07) 0.021 (0.53) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.120 (3.05) 0.090 (2.29) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier
ad664 rev. d C23C revision history 2/12rev. c to rev. d updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 12/91rev. b to rev. c ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10590-0-2/12(d)

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